525.642.81 - FPGA Design Using VHDL

Expanded Course Description

This course covers the design of digital systems using VHSIC Hardware Description Language (VHDL) and its implementation in Field Programmable Gate Arrays (FPGAs). This technology allows cost-effective unique system realizations by enabling design reuse and simplifying custom circuit design. The design tools are first introduced and used to implement basic circuits. More advanced designs follow, focusing on integrating the FPGA with external peripherals, simple data processing applications, utilizing soft-core processors, and using intellectual property (IP) cores.

No specific course is required as a pre-requisite. However, a solid understanding of digital logic fundamentals is required.

Course Structure

The course content is divided into modules which can be accessed by clicking Course Modules on the left menu. A module will have several sections including the overview, content, readings, discussions, and assignments. You are encouraged to preview all sections of the module before starting. Most modules run for a period of seven (7) days, exceptions are noted on the Course Outline page. You should regularly check the Calendar and Announcements for assignment due dates.

Course Topics

• Basic Combinatorial Logic
• VHDL Processes
• Sequential Design Problems using Processes
• Testbenches and VHDL Data Types
• Advanced Testbenches and Misc. Topics
• Operators in the Standard Numeric Library
• Finite State Machines
• Linear Feedback Shift Registers
• VHDL Parameterization and PicoBlaze
• Special Structures and Intellectual Property
• Timing Considerations in FPGAs
• Power Considerations in FPGAs
• Design Examples in VHDL

Course Goals

This course covers the design of digital systems using VHDL and its implementation in FPGAs. By the end of this course, you will be able to describe a system using synthesizable VHDL code, synthesize the design and map it onto an FPGA for verification. You will also acquire the skillset to utilize the Xilinx Vivado synthesis tools as well as the Xilinx Vivado simulator to verify the behavioral performance of the designs under test.

Course Learning Outcomes (CLOs)

• Translate a functional system description into appropriate digital blocks coded in VHDL.
• Perform synthesis, place-and-route, and map a digital design onto a target FPGA.
• Describe the behavior and performance of designs targeting FPGAs.
• Implement Finite State Machines (FSMs) to solve digital design problems.
• Utilize the Nexy's development board to solve common design problems in the Xilinx Vivado environment.
• Simulate the behavior of VHDL designs using test benches written in VHDL and simulated using Vivado Simulator.

Textbooks

The textbook for this course is highly recommended and will be referenced for further reading in many of the modules.   This course will reference the 3rd edition, however, the 2nd edition may be used at the student’s discretion.

Rushton, A. (2011). VHDL for logic synthesis (3rd ed.). Hoboken, NJ: John Wiley & Sons, Inc.

Other Materials & Online Resources

Required Hardware

Each registered student will be assigned an FPGA development board at the beginning of the semester. Each student is responsible for getting access to a VGA monitor with VGA cable and an oscilloscope for some of the labs.

If you only have access to an HDMI monitor, please email the instructor for options that can be used to interface to the development board.

Note: If you are registered for the course and receive a development board, you are expected to return the development board to the EP program, when the course completes for the semester or when the student leaves the course.

Required Software

Xilinx Vivado

You will need access to a recent version of Xilinx Vivado 2022.1 or newer (DO NOT install ISE). You can download the Xilinx Vivado ML Standard from: http://www.xilinx.com/support/download.html

I also recommend starting with the master constraints file for the development board.  You can download a copy of that here: https://github.com/Digilent/digilent-xdc/blob/master/Nexys-4-DDR-Master.xdc

Student Coursework Requirements

It is expected that each module will take approximately 12–16 hours per week to complete. Here is an approximate breakdown: reading the assigned sections of the texts (approximately 1–2 hours per week) as well as some outside reading, listening to the audio annotated slide presentations (approximately 1–2 hours per week), and working on lab assignments (approximately 10–12 hours per week).

This course will consist of four basic student requirements:

1. Preparation and Participation (Module Discussions) (10% of Final Grade Calculation)

You are responsible for reading all assigned material and being prepared for discussion. The majority of readings are from datasheets and manuals.

Part one of your grade for module discussion is to post your initial response to the discussion questions by the weekend for that module week.  Make this a new thread under the weekly Module Discussion Forum. Posting a response to the discussion question is part one of your grade for module discussions (i.e., Timeliness).

Part two of your grade for module discussion is your interaction (i.e., responding to classmate postings with thoughtful responses) with at least two classmates (i.e., Critical Thinking). Just posting your response to a discussion question is not sufficient; I would like you to interact with your classmates. Be detailed in your postings and in your responses to your classmates' postings. Feel free to agree or disagree with your classmates. Please ensure that your postings are civil and constructive.  The final grade for this will be decided by the instructor at the end of the semester.

I will monitor module discussions and will respond to some of the discussions as discussions are posted. In some instances, I will summarize the overall discussions and post the summary for the module.  Note that not every module has a question posted by the instructor.  In some cases, you are encouraged to post your own questions, if you have any, and other students are encouraged to respond.

Evaluation of preparation and participation is based on contribution to discussions.

Preparation and participation is evaluated by the following grading elements:

1. Preparation (5% of final grade), with 5/5 being the highest weighting 5 = Responds in detail to discussion question by the weekend module officially starts 4 = Responds briefly to discussion question by the weekend the module officially starts or    responds in detail after the weekend the module officially starts 3 = Responds briefly to discussion question after the weekend the module officially starts 2 = Responds in detail the discussion question after due date 1 = Responds briefly to discussion question after due date 0 = Does not respond to discussion topic by due date
2. Participation (5% of final grade), with 5/5 being the highest weighting 5 = Responds to 15 or more other posts throughout the semester 4 = Responds to 10 to 14 other posts throughout the semester 3 = Responds to 7 to 9 other posts throughout the semester 2 = Responds to 4 to 6 other posts throughout the semester 1 = Responds to 3 or less other posts throughout the semester 0 = Does not respond to posts throughout the semester

2. Lab Assignments (45% of Final Grade Calculation)

Assignments are referred to as lab assignments even though you don’t need an actual lab to work through them; you can work on your assignments in your office (if permitted) or at home. Lab assignments are given to you every week or every other week and are graded out of 100 points per assignment. I will give you the design requirements and you will construct a design in VHDL. You will then implement the design on the assigned development board for verification. Unless otherwise specified, each assignment will count equally towards the cumulative 45% of the class grade. Assignment submissions will include VHDL source files, XDC files, bit files as well as document files that include a documented report for each assignment. Remember that all Figures and Tables in your documents should be captioned and labeled appropriately. All files for each submission must be zipped together into a single project file and submitted via Canvas.

There will be one group assignment near the end of the semester which will utilize a smaller group environment/discussion to work through a more advanced project.  This submission will be equal to one lab assignment in weight, however, the grading will be based on participation as much as on the working final design.

All assignments are due according to the dates in the Calendar.

Late submissions by more than one week past the due date will not be accepted.  This includes assignments submitted late due to work-related travel.  Each late assignment will be reduced by 5 points of the possible 100 points.  It is the students’ responsibility to make sure they can manage their course work with their professional work.  If there are extenuating circumstances (such as medical emergencies) which make it impossible for you to get the assignment submitted within one week after the due date, then there will be no late penalty.  Points for incomplete assignments are awarded based on the level of effort and level of completeness.  The following is a guideline for points awarded for incomplete assignment submissions and is left to the discretion of the instructor:

• Non-synthesizable VHDL code: 50 points maximum per assignment
• Synthesizable VHDL resulting in a bit file, but design does not meet lab specifications: 65 points minimum per assignment. Additional points added for each listed lab requirement that is met.

Lab assignments, except for the final group assignment, are to be completed independently. Helping each other with tool-related problems, class material, or general VHDL knowledge is allowed and encouraged using the discussion forum. Copying assignments from other students or from the Web is not allowed. Any unauthorized copying of VHDL code from classmates or from the web will result in a zero for that assignment for both students and will be reported to the department chair.  Exceptions to this are using snippets of code I present in the modules as partial solutions to the assignments.

Assignments are to be well documented and appropriately designed. Simply getting the design to meet requirements for demonstration is not grounds for 100 points. The design should be done in a well-organized, understandable way, with appropriate comments. After the first assignment, I will often ask that the design should always be accompanied by a block diagram of your design – this should be developed BEFORE you start to implement your design. Analyzing the FPGA resource utilization for each assignment is necessary and required.

Each lab assignment lists several items I will look for when evaluating your submissions. Meeting all items may not guarantee a complete grade. It is my discretion how points are awarded, or deducted, for each lab assignment. For example, bugs not specifically detailed in the lab description are still considered as bugs. Copying and pasting the resource utilization summary without analyses is not acceptable.

The combination of all these factors plays a role in determining the lab grade.

Lab Assignments are graded as follows: (weighted out of 100/100 points)

100–90 = Design submitted on time that completely meets ALL specifications outlined in the assignment and is free of bugs. The student also carried out the following for each lab assignment:

• Implemented a well-organized design
• Included well-commented VHDL code
• Included a block diagram of the design
• Analyzed the design by estimating and studying the resource utilization
• Constructed a well-organized report

89–80 = A majority of the design requirements are met and may include a few bugs the instructor happens to notice. Points can be deducted for poorly coded or poorly commented VHDL; even if the design works fine on the FPGA. Points can also be deducted for incomplete analyses, reports or missing block diagrams.

79–70 = Design partially works with at least half of the specifications met. Submission does not include design analyses, block diagrams or report. VHDL coding style does not follow good design practices and lack s comments.

3. Quizzes (10% of Final Grade Calculation)

Brief quizzes will be assigned for each module. The quizzes cover, in a very straight-forward manner, concepts presented in the module lectures. The lowest quiz score will be dropped. There will be a quiz for every module unless told otherwise.

Quizzes are graded as follows: (weighted out of 10/10)

10 – 8 = A

7 – 6 = B

6 – 5 = C

Late quiz submissions will not be accepted.  As a result, I will drop the lowest quiz grade.

4. Exam (35% of Final Grade Calculation)

The only exam for the course will be available in the week of Module 10 and is referred to as a Midterm Exam. You will have a two day block of time to download and complete the exam. The midterm will cover concepts and material covered up to and including Module 9. This includes material covered in lecture videos, class discussions (forums), quizzes, lab assignments, assigned and optional readings, hosted videos and recorded office hours. You may use your course notes and module materials for the exam. Since this is a course that discusses VHDL code and syntax in detail, you will be expected to write VHDL code using correct syntax to solve some of the problems on the exam.

Grading Policy

Assignments are due according to the dates posted in your Canvas course site. You may check these due dates in the Course Calendar or the Assignments in the corresponding modules. I will post grades one week after assignment due dates for assignments turned in on time. If you do not receive a grade on an assignment that you have turned in, please ask of its whereabouts; it may need to be resubmitted.

Assignments are expected to be submitted using Canvas as indicated in the assignment instructions; it will be considered late if it is received after that time. Special circumstances (e.g., temporary lack of internet access) can be accommodated if you inform me in advance. Assignments that are unjustifiably late will have the grade reduced by 5 points per assignment for each week it is late.

Instructors generally do not directly grade spelling and grammar. However, egregious violations of the rules of the English language will be noted without comment. Consistently poor performance in either spelling or grammar is taken as an indication of poor written communication ability that may detract from your grade.

A grade of A indicates achievement of consistent excellence and distinction throughout the course—that is, conspicuous excellence in all aspects of assignments and discussion in every week.

A grade of B indicates work that meets all course requirements on a level appropriate for graduate academic work. These criteria apply to both undergraduates and graduate students taking the course.

EP uses a +/- grading system (see “Grading System”, Graduate Programs catalog, p. 9).

Final grades for this course are based on the following scale

Final grades for this course will be determined by the following weighting:

Late Assignment Submissions Due to Travel

It happens that students will have work-related travel plans and will be in a situation where they cannot work on a particular assignment due to lack of internet access or the lack of personal time due to extended work days or both. If you know you will have travel plans, please inform the instructor ahead of time. While difficult, it is possible to catch up with the course work and material due to missing one week of class. However, missing more than one week of class will make it very difficult to catch up and submit subsequent assignments on time. It is the students’ responsibility to manage their travel plans during the semester and to catch up on all course material. The policy remains that assignment submitted more than one week after the due date will not be accepted.

Course Policies

Please make sure to notify the instructor well in advance for any travel or time away that will need to be considered for the course.  If you can't submit a lab assignment on time or are not available during the midterm weekend, the instructor will need plenty of advance notice to accommodate.

Academic Policies

Deadlines for Adding, Dropping and Withdrawing from Courses

Students may add a course up to one week after the start of the term for that particular course. Students may drop courses according to the drop deadlines outlined in the EP academic calendar (https://ep.jhu.edu/student-services/academic-calendar/). Between the 6th week of the class and prior to the final withdrawal deadline, a student may withdraw from a course with a W on their academic record. A record of the course will remain on the academic record with a W appearing in the grade column to indicate that the student registered and withdrew from the course.

Academic Misconduct Policy

All students are required to read, know, and comply with the Johns Hopkins University Krieger School of Arts and Sciences (KSAS) / Whiting School of Engineering (WSE) Procedures for Handling Allegations of Misconduct by Full-Time and Part-Time Graduate Students.

This policy prohibits academic misconduct, including but not limited to the following: cheating or facilitating cheating; plagiarism; reuse of assignments; unauthorized collaboration; alteration of graded assignments; and unfair competition. Course materials (old assignments, texts, or examinations, etc.) should not be shared unless authorized by the course instructor. Any questions related to this policy should be directed to EP’s academic integrity officer at ep-academic-integrity@jhu.edu.

Students with Disabilities - Accommodations and Accessibility

Johns Hopkins University values diversity and inclusion. We are committed to providing welcoming, equitable, and accessible educational experiences for all students. Students with disabilities (including those with psychological conditions, medical conditions and temporary disabilities) can request accommodations for this course by providing an Accommodation Letter issued by Student Disability Services (SDS). Please request accommodations for this course as early as possible to provide time for effective communication and arrangements.

For further information or to start the process of requesting accommodations, please contact Student Disability Services at Engineering for Professionals, ep-disability-svcs@jhu.edu.

Student Conduct Code

The fundamental purpose of the JHU regulation of student conduct is to promote and to protect the health, safety, welfare, property, and rights of all members of the University community as well as to promote the orderly operation of the University and to safeguard its property and facilities. As members of the University community, students accept certain responsibilities which support the educational mission and create an environment in which all students are afforded the same opportunity to succeed academically. 

For a full description of the code please visit the following website: https://studentaffairs.jhu.edu/policies-guidelines/student-code/

Classroom Climate

JHU is committed to creating a classroom environment that values the diversity of experiences and perspectives that all students bring. Everyone has the right to be treated with dignity and respect. Fostering an inclusive climate is important. Research and experience show that students who interact with peers who are different from themselves learn new things and experience tangible educational outcomes. At no time in this learning process should someone be singled out or treated unequally on the basis of any seen or unseen part of their identity. 
 
If you have concerns in this course about harassment, discrimination, or any unequal treatment, or if you seek accommodations or resources, please reach out to the course instructor directly. Reporting will never impact your course grade. You may also share concerns with your program chair, the Assistant Dean for Diversity and Inclusion, or the Office of Institutional Equity. In handling reports, people will protect your privacy as much as possible, but faculty and staff are required to officially report information for some cases (e.g. sexual harassment).

Course Auditing

When a student enrolls in an EP course with “audit” status, the student must reach an understanding with the instructor as to what is required to earn the “audit.” If the student does not meet those expectations, the instructor must notify the EP Registration Team [EP-Registration@exchange.johnshopkins.edu] in order for the student to be retroactively dropped or withdrawn from the course (depending on when the "audit" was requested and in accordance with EP registration deadlines). All lecture content will remain accessible to auditing students, but access to all other course material is left to the discretion of the instructor.