525.677.81 - Hardware Architectures for DSP Algorithms

Electrical and Computer Engineering
Fall 2025

Description

This course introduces techniques for refining signal processing algorithms to hardware implementations described using a hardware descriptive language. Students design, model and simulate signal processing algorithms through different levels of hardware refinement. Hardware structures for finite impulse filter (FIR), infinite impulse filters (IIR) and adaptive equalizers are studied and analyzed throughout the course. Multi-rate and multi-signal concepts are covered during the course and these concepts are applied to different signal processing techniques. Cut-set retiming methods to generate parallel and systolic array filtering structures are also covered in the course. By the end of the course, students are able to refine a signal processing algorithm targeting hardware platforms such as field programmable gate arrays (FPGA). An understanding of digital signal processing and VHDL for FPGAs is required for this course.

Expanded Course Description

Prerequisites

525.627 Digital Signal Processing and 525.642 FPGA Design Using VHDL, or equivalent to each of these courses.

Instructor

Profile photo of Ramsey Hourani.

Ramsey Hourani

rhouran5@jhu.edu

Course Structure

The course content is organized into modules, accessible by clicking Modules on the course menu. A module has several sections including the overview, content, readings, discussions, and assignments. You are encouraged to preview all sections of the module before beginning. Most modules run for seven (7) days; exceptions are noted in the Course Outline. Check the Calendar and Announcements regularly for assignment due dates.

Course Topics

Course Goals

Describe a signal processing algorithm at different levels of hardware abstractions, and refine it to different hardware implementations suitable for field programmable gate arrays (FPGA).

Course Learning Outcomes (CLOs)

Textbooks

There are no required textbooks.

Required Software

MATLAB
You will need access to a recent version of MATLAB. A license is provided at no cost to you through JHU.
Visit the JHU IT Services Portal. Log in with your JHED ID and type “MATLAB” in the search bar. Click on “MATLAB for Students” in the search results and follow the instructions provided.

SystemC version: 2.3.4
The SystemC zip file will be provided to you for installation. You are expected to know how to install SystemC on your computer.

Xilix Vivado
Version 2018.1 or newer will be needed for this course to synthesize the VHDL designs. You are expected to know how to install Vivado on your computer.

Student Coursework Requirements

Each module will take approximately 7–10 hours per week to complete. Here is an approximate breakdown: watching video lectures (approximately 1–2 hours per week), working on assignments (approximately 4–6 hours per week), attending weekly office hours (approximately 1 hour per week), and contributing to the discussion posts (approximately 1 hour per week).

This course will consist of the following basic student requirements:

Preparation and Participation (10% of Final Grade Calculation)

You are responsible for carefully reading all assigned material and preparing for discussions. Most readings are from the course text. Additional reading may be assigned to supplement the text readings.

Post your initial response to the discussion questions by the end of day 3 for that module week. Posting a response to the discussion question is part one of your grade for module discussions (i.e., Timeliness).

Part two of your discussion grade is interaction (i.e., thoughtful responses to classmate posts) with at least two classmates (i.e., Critical Thinking). Just posting your response to a discussion question is not sufficient; you should interact with your classmates. Be detailed in your posts and your responses to your classmates' postings. You may agree or disagree with your classmates, but ensure you are civil and constructive. I will monitor module discussions and will respond to some of them as they are posted. Evaluation of preparation and participation is based on contribution to discussions.

Preparation and participation are evaluated by the following grading elements:

Assignments (40% of Final Grade Calculation)

Assignments primarily focus on designing and verifying hardware structures for DSP algorithms using MATLAB, SystemC, and VHDL. Include a cover sheet with your name and assignment identifier. Also include your name and a page number indicator (i.e., page x of y) on each page of your submissions. Each problem should have the problem statement, assumptions, computations, and conclusions/discussion delineated. All Figures and Tables should be captioned and appropriately labeled.

Assignments are due according to the dates in the Calendar. Late submissions by more than one week past the due date will not be accepted. This includes assignments submitted late due to work-related travel. Each late assignment will be reduced by 5 points of the possible 100 points. It is the students’ responsibility to ensure they can manage their coursework alongside their professional work. If there are extenuating circumstances (such as medical emergencies) that make it impossible to submit the assignment within a week after the due date, there will be no late penalty. Points for incomplete assignments are awarded based on the level of effort and level of completeness. 

Assignments must be completed independently. Helping each other with course tool-related problems, class content, or general MATLAB, SystemC, and VHDL knowledge is permitted and encouraged in the discussion forum. Copying assignments from other students, the Web, or using Generative AI tools is prohibited. Violations will result in a zero for that assignment for both students and will be reported to the department chair. Exceptions to this are using snippets of code I present in the modules as partial solutions to the assignments.

Assignments must be well-documented, appropriately designed, and coded. Simply getting the design to meet requirements is not grounds for 100 points. The design and code should be well-organized, understandable, with appropriate comments.

Each assignment lists several items that need to be submitted. Meeting all items may not guarantee a complete grade. I reserve the right to award or deduct points for each assignment. For example, code bugs not specifically detailed in the assignment are still considered bugs. Copying and pasting the FPGA resource utilization summary (for example, without analysis) is unacceptable.

The combination of all these factors plays a role in determining the assignment grades.

Assignments are graded as follows: (weighted out of 100/100 points)

100–90 = Design submitted on time that completely meets ALL specifications outlined in the assignment. The student also carried out the following for each assignment:

89–80 = A majority of the design requirements are met and may include a few bugs that the instructor happens to notice. Points can be deducted for poorly coded or poorly commented MATLAB, SystemC, and VHDL; even if the design works as expected. Points can also be deducted for incomplete analyses, reports, or missing block diagrams.

79–70 = Design partially works with at least half of the specifications met. Submission does not include design analyses, block diagrams, or report. Coding style does not follow good design practices and lacks comments.

Course Project (30% of Final Grade Calculation)

The course project will be assigned after module 10 (midterm exam) and evaluated by the following grading elements:

  1. Project design completed using MATLAB, SystemC, and VHDL (20%)
  2. All MATLAB, SystemC, and VHDL code adheres to good coding and design styles, and includes clear and descriptive comments (20%)
  3. Submission requirements met for each part of the project (20%)
  4. Clear plots and diagrams are used throughout the project write-up (20%)
  5. A well-written report that clearly describes the project flow (20%)

Exam (20% of Final Grade Calculation)

The only exam for the course—the Midterm, will be available in the week of Module 10. You will have a two-day block of time to download and complete it. The midterm exam will cover concepts and material up to and including Module 9. This includes material covered in the video lectures, class discussions (forums), assignments, and recorded office hours. You may use your course notes and module materials for the exam. Since this is a course that discusses MATLAB, SystemC, and VHDL code and syntax in detail, you are expected to write code using correct syntax to solve some of the problems on the exam.

Grading Policy

Assignments are due according to the dates posted in the Canvas course site. You may check these due dates in the Course Calendar or the Assignments in the corresponding modules. I will post grades one week after the assignment due dates. Example grades are posted two weeks after the exam is submitted.

I generally do not directly grade spelling and grammar. However, egregious violations of the rules of the English language will be noted without comment. Consistently poor performance in either spelling or grammar is taken as an indication of poor written communication ability that may detract from your grade.

A grade of A indicates achievement of consistent excellence and distinction throughout the course—that is, conspicuous excellence in all aspects of assignments and discussion in every week. A grade of B indicates work that meets all course requirements on a level appropriate for graduate academic work. These criteria apply to both undergraduates and graduate students taking the course.

EP uses a +/- grading system (see “Grading System”, Graduate Programs catalog, p. 10).

Score RangeLetter Grade
100-98= A+
<97-94= A
<93-90= A−
<89-87= B+
<86-83= B
<82-80= B−
<79-77= C+
<76-73= C
<72-70= C−
<69-67= D+
<66-63= D
<63= F


Final grades will be determined by the following weighting:

Item

% of Grade

Preparation and Participation

10%

Assignments

40%

Course Project

30%

Exam (Midterm)

20%

Course Policies

Late Assignment Submissions Due to Travel: You may have work-related travel plans and/or have a situation where you cannot work on a particular assignment due to lack of internet access, personal time as a result of extended work days, or both. If you know you will have travel plans, please inform the instructor ahead of time. While difficult, it is possible to catch up with the coursework and material due to missing one week of class. However, missing more than one week of class will make it very difficult to catch up and submit subsequent assignments on time. It is the students’ responsibility to manage their travel plans during the semester and to catch up on all course material. The policy remains that assignments submitted more than one week after the due date will not be accepted.

Academic Policies

Deadlines for Adding, Dropping and Withdrawing from Courses

Students may add a course up to one week after the start of the term for that particular course. Students may drop courses according to the drop deadlines outlined in the EP academic calendar (https://ep.jhu.edu/student-services/academic-calendar/). Between the 6th week of the class and prior to the final withdrawal deadline, a student may withdraw from a course with a W on their academic record. A record of the course will remain on the academic record with a W appearing in the grade column to indicate that the student registered and withdrew from the course.

Academic Misconduct Policy

All students are required to read, know, and comply with the Johns Hopkins University Krieger School of Arts and Sciences (KSAS) / Whiting School of Engineering (WSE) Procedures for Handling Allegations of Misconduct by Full-Time and Part-Time Graduate Students. This policy prohibits academic misconduct, including but not limited to the following: cheating or facilitating cheating; plagiarism; reuse of assignments; unauthorized collaboration; alteration of graded assignments; and unfair competition. Course materials (old assignments, texts, or examinations, etc.) should not be shared unless authorized by the course instructor. Any questions related to this policy should be directed to EP’s academic integrity officer at ep-academic-integrity@jhu.edu.

Students with Disabilities - Accommodations and Accessibility

Johns Hopkins University is committed to providing welcoming, equitable, and accessible educational experiences for all students. If disability accommodations are needed for this course, students should request accommodations through Student Disability Services (SDS) as early as possible to provide time for effective communication and arrangements.  For further information about this process, please refer to the SDS Website.

Student Conduct Code

The fundamental purpose of the JHU regulation of student conduct is to promote and to protect the health, safety, welfare, property, and rights of all members of the University community as well as to promote the orderly operation of the University and to safeguard its property and facilities. As members of the University community, students accept certain responsibilities which support the educational mission and create an environment in which all students are afforded the same opportunity to succeed academically.  For a full description of the code please visit the following website: https://studentaffairs.jhu.edu/policies-guidelines/student-code/

Classroom Climate

JHU is committed to creating a classroom environment that values the diversity of experiences and perspectives that all students bring. Everyone has the right to be treated with dignity and respect. Fostering an inclusive climate is important. Research and experience show that students who interact with peers who are different from themselves learn new things and experience tangible educational outcomes. At no time in this learning process should someone be singled out or treated unequally on the basis of any seen or unseen part of their identity.    If you have concerns in this course about harassment, discrimination, or any unequal treatment, or if you seek accommodations or resources, please reach out to the course instructor directly. Reporting will never impact your course grade. You may also share concerns with your program chair, the Assistant Dean for Diversity and Inclusion, or the Office of Institutional Equity. In handling reports, people will protect your privacy as much as possible, but faculty and staff are required to officially report information for some cases (e.g. sexual harassment).

Course Auditing

When a student enrolls in an EP course with “audit” status, the student must reach an understanding with the instructor as to what is required to earn the “audit.” If the student does not meet those expectations, the instructor must notify the EP Registration Team [EP-Registration@exchange.johnshopkins.edu] in order for the student to be retroactively dropped or withdrawn from the course (depending on when the "audit" was requested and in accordance with EP registration deadlines). All lecture content will remain accessible to auditing students, but access to all other course material is left to the discretion of the instructor.