525.742.8VL - System-on-a-Chip FPGA Design Laboratory

Expanded Course Description

This lab-oriented course will focus on the design of large-scale system-on-a-chip (SOC) solutions within field-programmable gate arrays (FPGAs). Modern FPGA densities and commercially available cores enable a single developer to design highly complex systems within a single FPGA. This class will provide the student with the ability to design and debug these inherently complex systems. Topics will include high-speed digital signal processing, embedded processor architectures, customization of soft-core processors, networking, and interfacing with high-speed devices. The optimum division of algorithms between hardware and software will be discussed, particularly the ability to accelerate software algorithms by building custom hardware. Many labs will center on a common architecture that includes signal processing algorithms in the FPGA fabric, controlled by an embedded processor that provides user interfaces and network communication.

Course Structure

This course is structured around a series of Lab assignments that build upon one another to demonstrate the component concepts and build toward the design and integration of complete system.   

Course meetings will consist of a lecture introducing the necessary concepts for the lab project being assigned followed by time where students can work on the projects while classmates and the instructor are available for discussion of any questions from the lecture, the assignment, or that arise during the project work, etc. Occasionally, for larger or more complex labs, students will be given two weeks to complete the assignment and the class meeting in between will be entirely dedicated to a working session.   

Modules in Canvas are associated with each lab or group of related labs.  These modules contain the lecture slides for the discussion, the laboratory assignments themselves, and any other associated materials.

Links to the Zoom class meetings and office hours will be accessible in Canvas.  Each class meeting will be recorded so that students may re-watch/review portions of interest as they complete the assignments and/or for students who are unable to attend a meeting live.  Recording links will be posted 

Course Topics

• System-on-chip Introduction
• Design of Hybrid Hardware / Software systems
• Standard SOC Interface Types
• Zynq SOC (Hard-Core Processing Systems)
• Effectively Debugging Large Scale Systems
• Signal Processing in FPGA Fabric for Software Defined Radio
  • Direct Digital Synthesis
  • FIR Filtering
  • Direct Digital Downconversion
• Packaging Custom IP
  
• Ethernet, TCP/IP
  
• Linux
• Special FPGA Structures (Serializers, Clock Synthesizers, DDR)
• Customizing Soft-Core Microprocessors
• High Level Synthesis

Course Goals

The goal of this course is to familiarize students with the skills needed to design, develop, debug and test complex systems built on single chip FPGA or ARM/FPGA processing systems. In order to achieve this goal we will discuss topics including how to break complex tasks into individual hardware and software components, reusability and sharing of these components, and advanced concepts in FPGA hardware design necessary to build these components.

Course Learning Outcomes (CLOs)

• Design and develop highly functional systems which reside on a single FPGA
• Effectively merge IP blocks and custom hardware to construct optimal systems
• Efficiently break down computational tasks into hardware and software components for an optimally flexible and high-performance system
• Gain experience with advanced topics in FPGA design: Managing clock domains, External high speed interfaces SERDES, Advanced debugging Internal Logic Analyzer (ILA), External memory interfacing SDR, DDR, SRAM, Working with IP Cores

Textbooks

not required

Other Materials & Online Resources

A relatively modern computer running Windows 10 or Linux.  The system should be capable of running Xilinx Vivado (the software used in the pre-requisite class, 525.642).  The class will require much larger FPGA designs, so 16GB of memory is highly recommended to minimize wait-times

Required Software

MS Teams 

For access to the discussion boards, you will need to use Microsoft Teams, which is linked from the class in Canvas.  Access to teams is provided with your JHED login. More information is available here: https://it.johnshopkins.edu/services/collaborationtools/Teams/.

I strongly recommend you install the standalone version of MS Teams on your computer and/or mobile devices. The web interface does not fully support all the capabilities of the system.   

Xilinx Vivado 2021.2 

Instructions to download and install Vivado and the necessary components are included in a tutorial that you will complete as part of the first assignment.  Please make sure you install version 2021.2, it is necessary that everyone in the class use the same version of the tools.

MATLAB (any recent version is acceptable) + Signal Processing Toolbox 

If you don’t already have a copy of Matlab with the signal processing toolbox, JHU provides a free “Total Academic Headcount” license to all students that provides access to Matlab/Simulink and all toolboxes (for academic use only).  Instructions are here:  https://johnshopkins.service-now.com/serviceportal?id=kb_article&sys_id=ae56b34637694b805e00efb2b3990ef2

Student Coursework Requirements

Lab Assignments (100% of Final Grade Calculation) 

Assignments are due according to the dates/times indicated on the assignment in MS Teams. Typically, this will be the start of the class meeting on the due date (i.e. 4:30PM on class day). I will attempt to return grades for each lab well prior to the due date for the following lab  

I will provide a detailed rubric to students along with each assignment. This rubric will specify the required features, functionality, documentation or other aspects of the completed and submitted project. Point values/weights associated with each of the above and partial credit opportunities are included. I attempt to make this very specific, so that in most cases you should be able to test your project and determine your approximate grade on your own before you submit it. If anything seems vague or unclear, please let me know ahead of time.

Grading Policy

As with other EP courses: 

• A grade of A indicates achievement of consistent excellence and distinction throughout the course. 
• A grade of B indicates work that meets all course requirements on a level appropriate for graduate academic work. These criteria apply to both undergraduates and graduate students taking the course. 

Final grades will be determined by the following weighting: 

Course Policies

Collaboration 

All assignments in this course are to be completed individually. There should be no copying/duplicating of code or other project materials between students. That said, I want this course to be a collaborative learning experience just like the projects you work on professionally. I encourage you to discuss your work with us and with your classmates through the MS Teams discussion boards. Talk about the problems you encounter. Help your classmates think about solutions to the problems they encounter. By using the discussion boards instead of one-on-one conversations your discussions are a benefit to the whole group and you benefit from the ideas of the whole group in return.   

Late Assignments 

Late assignments are not accepted for either part of Lab 1.  Throughout the remainder of the semester you may request an extra week to complete an assignment for a 10 point penalty on that assignment with no questions asked. You may also, of course, discuss individual circumstances such as work travel, unexpected events, etc. to request consideration for alternative arrangements. In either case, it is required that you notify me in advance of the submission deadline.

Academic Policies

Deadlines for Adding, Dropping and Withdrawing from Courses

Students may add a course up to one week after the start of the term for that particular course. Students may drop courses according to the drop deadlines outlined in the EP academic calendar (https://ep.jhu.edu/student-services/academic-calendar/). Between the 6th week of the class and prior to the final withdrawal deadline, a student may withdraw from a course with a W on their academic record. A record of the course will remain on the academic record with a W appearing in the grade column to indicate that the student registered and withdrew from the course.

Academic Misconduct Policy

All students are required to read, know, and comply with the Johns Hopkins University Krieger School of Arts and Sciences (KSAS) / Whiting School of Engineering (WSE) Procedures for Handling Allegations of Misconduct by Full-Time and Part-Time Graduate Students.

This policy prohibits academic misconduct, including but not limited to the following: cheating or facilitating cheating; plagiarism; reuse of assignments; unauthorized collaboration; alteration of graded assignments; and unfair competition. Course materials (old assignments, texts, or examinations, etc.) should not be shared unless authorized by the course instructor. Any questions related to this policy should be directed to EP’s academic integrity officer at ep-academic-integrity@jhu.edu.

Students with Disabilities - Accommodations and Accessibility

Johns Hopkins University values diversity and inclusion. We are committed to providing welcoming, equitable, and accessible educational experiences for all students. Students with disabilities (including those with psychological conditions, medical conditions and temporary disabilities) can request accommodations for this course by providing an Accommodation Letter issued by Student Disability Services (SDS). Please request accommodations for this course as early as possible to provide time for effective communication and arrangements.

For further information or to start the process of requesting accommodations, please contact Student Disability Services at Engineering for Professionals, ep-disability-svcs@jhu.edu.

Student Conduct Code

The fundamental purpose of the JHU regulation of student conduct is to promote and to protect the health, safety, welfare, property, and rights of all members of the University community as well as to promote the orderly operation of the University and to safeguard its property and facilities. As members of the University community, students accept certain responsibilities which support the educational mission and create an environment in which all students are afforded the same opportunity to succeed academically. 

For a full description of the code please visit the following website: https://studentaffairs.jhu.edu/policies-guidelines/student-code/

Classroom Climate

JHU is committed to creating a classroom environment that values the diversity of experiences and perspectives that all students bring. Everyone has the right to be treated with dignity and respect. Fostering an inclusive climate is important. Research and experience show that students who interact with peers who are different from themselves learn new things and experience tangible educational outcomes. At no time in this learning process should someone be singled out or treated unequally on the basis of any seen or unseen part of their identity. 
 
If you have concerns in this course about harassment, discrimination, or any unequal treatment, or if you seek accommodations or resources, please reach out to the course instructor directly. Reporting will never impact your course grade. You may also share concerns with your program chair, the Assistant Dean for Diversity and Inclusion, or the Office of Institutional Equity. In handling reports, people will protect your privacy as much as possible, but faculty and staff are required to officially report information for some cases (e.g. sexual harassment).

Course Auditing

When a student enrolls in an EP course with “audit” status, the student must reach an understanding with the instructor as to what is required to earn the “audit.” If the student does not meet those expectations, the instructor must notify the EP Registration Team [EP-Registration@exchange.johnshopkins.edu] in order for the student to be retroactively dropped or withdrawn from the course (depending on when the "audit" was requested and in accordance with EP registration deadlines). All lecture content will remain accessible to auditing students, but access to all other course material is left to the discretion of the instructor.