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525.659.81 - Mixed-Mode VLSI Circuit Design

Electrical and Computer Engineering

Spring 2024

Description

This course focuses on transistor-level design of mixed-signal CMOS integrated circuits. After reviewing fundamentals of MOSFET operation, the course will cover design of analog building blocks such as current-mirrors, bias references, amplifiers, and comparators, leading up to the design of digital-to-analog and analog-to-digital converters. Aspects of subthreshold operation, structured design, scalability, parallelism, low power-consumption, and robustness to process variations are discussed in the context of larger systems. The course will include use of Cadence design software to explore transistor operation and to perform functional-block designs, in the process of incrementally designing a data-converter front-end. Prerequisite(s): Familiarity with MOSFET and transistor level circuit design fundamentals.

Instructor

Radmil Elkis

relkis.jhu@gmail.com

Course Structure

The course materials are divided into modules which can be accessed by clicking Course Modules on the left menu. A module will have several sections, including the overview, content, readings, discussions, and assignments. You are encouraged to preview all sections of the module before starting. Most modules run for a period of seven (7) days. We will begin our week on Wednesday and end on Tuesday at 11:59 PM EST. You should regularly check the Calendar and Announcements for assignment due dates.

Course Goals

This course will cover the fundamentals of transistor-level circuit design, preparing the students to design blocks for very-large scale integrated circuits (VLSI). The students will learn the essentials of transistor- level design at different abstraction levels, from device fabrication and modeling, to circuit topologies, to circuit architectures of systems such as data converters. Analytical approaches will be supplemented with simulations, allowing the students to become familiar with using the industry-standard software tool suite, Cadence, to analyze and design transistor-level circuits.

Course Learning Outcomes (CLOs)

Describe fundamentals of semiconductor physics and silicon technology fabrication.
Describe and apply fundamentals of FET operation across various regions.
Apply small-signal modeling to analyze functionality of FET integrated circuits.
Describe, analyze and design single-stage amplifiers.
Analyze and design current mirrors for various applications.
Analyze and design FET translinear circuits using the sub-threshold region of operation.
Analyze and design differential amplifiers, operational trans-impedance amplifiers (OTAs), and operational amplifiers (Op-Amps).
Analyze and design voltage and current references with desired temperature characteristics.
Analyze and design basic switched-capacitor circuits.
Describe and compare various data converter architectures.
Describe and apply data converter performance metrics.
Describe, analyze and design data converter building blocks.
Understand integrated-circuit simulation analyses and approaches, and apply them to the design of transistor-level circuits within the industry-standard Cadence design tool suite.

Textbooks

Required

The following textbook is required, and will serve as a source of both reading assignments and problem sets for the course. I think you’ll find that this textbook strikes a very good balance in offering intuitive explanations, advanced concepts, and valuable circuittopology approaches. Being a very new edition, it also contains up-to-date information on new nanometer-process-node design and processing considerations. For anyone pursuing transistor-level circuit design as a career, it will likely become a useful reference.

Razavi, B. (2017). Design of Analog CMOS Integrated Circuits (2nd. Edition). McGraw-Hill Publishing Company.

ISBN 13: 978-0-07-252493-2
ISBN-10: 0-07-252493-6

Required Software

The course will involve simulation assignments in Cadence software, which has become an industry standard used by virtually all companies in the integrated circuit design area. Access to simulation licenses for this software will be provided by Johns Hopkins University. The tool will be accessed by the students remotely, by logging into JHU servers. Information on the terminal software and how to access the JHU servers that can be accessed will be given out during the first week of the class.

More detailed instructions on remote access of machines and use of Cadence will be provided in the Course Information section of your Canvas course.

Student Coursework Requirements

It is expected that each module will take approximately 7–10 hours per week to complete. Here is an approximate breakdown:

viewing the online lectures; the number of lectures per module varies from 1 to 3 (approximately 1-2 hours per week).
reading the assigned sections of the required textbook (approximately 2–3 hours per week).
completing written problem sets, typically assigned from the textbook, though some may be provided in a different format (approximately 1–2 hours per week).
completing the Cadence simulation assignment (approximately 1–2 hours per week).
completing readings assigned as part of the “discussion” assignment, and contributing to the asynchronous online discussion forum to address the topics/questions of the week (approximately 1–2 hours per week).

This course will consist of four basic student requirements:

Preparation and Participation (Module Discussions) (15% of Final Grade Calculation)

You are responsible for carefully reading all assigned material and being prepared for discussion. The majority of readings are from the course text. Additional reading may be assigned to supplement text readings.

Post your initial response to the discussion questions by the evening of day 3 for that module week. Posting a response to the discussion question is part one of your grade for module discussions (i.e., Timeliness).

Part two of your grade for module discussion is your interaction (i.e., responding to classmate postings with thoughtful responses) with at least two classmates (i.e., Critical Thinking). Just posting your response to a discussion question is not sufficient; please interact with your classmates. Be detailed in your postings and in your responses to your classmates' postings. Feel free to agree or disagree with your classmates. Please ensure that your postings are civil and constructive.

I will monitor module discussions and will respond to some of the discussions as discussions are posted. In some instances, I will summarize the overall discussions and post the summary for the module.

Evaluation of preparation and participation is based on contribution to discussions. Preparation and participation isevaluated by the following grading elements:

Timeliness (50%)
Critical Thinking (50%)

Preparation and participation is graded as follows:

100–90 = A—Timeliness [regularly participates; all required postings; early in discussion; throughout the discussion]; Critical Thinking [rich in content; full of thoughts, insight, and analysis].

89–80 = B—Timeliness [frequently participates; all required postings; some not in time for others to read and respond];Critical Thinking [substantial information; thought, insight, and analysis has taken place].

79–70 = C—Timeliness [infrequently participates; all required postings; most at the last minute without allowing for response time]; Critical Thinking [generally competent; information is thin and commonplace].

<70 = F—Timeliness [rarely participates; some, or all required postings missing]; Critical Thinking [rudimentary and superficial; no analysis or insight is displayed].

Written Problem Assignments (20% of Final Grade Calculation)

Weekly problem assignments will typically include 1-2 problems. Include a cover sheet with your name and assignment identifier. Also include your name and a page number indicator (i.e., page x of y) on each page of your submissions. Each solution should state any assumptions, show the complete computations, clearly show and underline the final result, and explain the solution when applicable. All Figures and Tables should be captioned and labeled appropriately.

All assignments are due according to the dates in the Calendar.

Assignment submission format:

Please use the following document name syntax: Hk1_<last_name>_<date_submitted> (example: Hk1_Elkis_05Jan16.pdf)

Single-file PDF of the scanned-in assignment, including

answers to questions typed or legibly hand-written
any required plots hand-sketched
- be sure to label all plots with axis variables and units
- if applicable, note and label important break-points

Late submissions will be reduced by one letter grade for each week late (no exceptions without prior coordination with the instructors).

The written assignments are graded as follows:

100–90 = A—All parts of question are addressed; all assumptions are clearly stated; all intermediate derivations and calculations are provided; answer is technically correct and is clearly indicated; answer precision and units are appropriate.

89–80 = B—All parts of question are addressed; all assumptions are clearly stated; some intermediate derivations andcalculations are provided; answer is technically correct and is indicated; answer precision and units are appropriate.

79–70=C—Most parts of question are addressed; assumptions are partially stated; few intermediate derivations andcalculations are provided; answer is not technically correct but is indicated; answer precision and units are indicated but inappropriate.

<70=F—Some parts of the question are addressed; assumptions are not stated; intermediate derivations and calculations are not provided; the answer is incorrect or missing; the answer precision and units are inappropriate or missing.

Cadence Simulation Assignments (35% of Final Grade Calculation)

Cadence simulation assignments will be assigned on a weekly basis. Students not familiar with use of the Cadencesoftware are expected to make use of tutorials and help-files available in the software kit, to learn the basics of using the Analog Design Environment (ADE) software for transistor-level simulations. Detailed instructions will also be provided for the first several assignments, to help students come up to speed in using the software.

Toward the end of the course, the functional blocks designed in Cadence assignments throughout the course will be combined to build a design project of a data-converter front-end. Since the final design project will require all constituent blocks to be functional, students are expected to incorporate the instructor’s feedback to make any necessary adjustments or corrections to each module’s Cadence assignment, after it is graded.

Cadence assignment submission format:

Please use the following document name syntax: Cadence<num>_<last_name>_<date_submitted> (example:Cadence1_Elkis_05Jan16.pdf)

Single-file PDF of the scanned-in assignment, including

Cadence schematic screenshot pasted
Cadence results plot screenshots pasted
Answers to questions typed or legibly hand-written The Cadence simulationassignments are graded as follows:

100–90 = A—All parts of the assignment are addressed; the schematic is correctly constructed and clearly shown, with all key nodes are carefully labeled; all results are correctly plotted and labeled; explanations and answers are technically correct and clearly indicated; answer precision and units are appropriate.

89–80 = B— All parts of the assignment are addressed; the schematic is correctly constructed and clearly shown, with some key nodes are carefully labeled; most results are correctly plotted and labeled; most explanations and answers aretechnically correct and clearly indicated; answer precision and units are predominantly appropriate.

79–70=C— Most parts of the assignment are addressed; the schematic construction is partially correct and clearly shown, with some key nodes are carefully labeled; results are plotted and labeled, but not correctly; explanations and answers are not technically correct, but clearly indicated; answer precision and units are indicated but inappropriate

<70=F— Some parts of the assignment are addressed; the schematic construction is not clearly shown or fundamentally flawed; results are incorrectly plotted and labeled, or missing; explanations and answers are not technically correct, or missing; answer precision and units are inappropriate or missing.

Exams (30% of Final Grade Calculation, combined from 15% for Midterm and 15% for Final)

The midterm exam will be available on Monday in Module 8, and the final exam will be available on Monday in Module 14.Each exam will be due by 9PM on Friday. You may use the course text to complete the exams.

Exam questions are graded as follows:

Grading Policy

Assignments are due according to the dates posted in your Canvas course site. You may check these due dates in the Course Calendar or the Assignments in the corresponding modules. I will post grades one week after assignment due dates.

I generally do not directly grade spelling and grammar. However, egregious violations of the rules of the English language will be noted without comment. Consistently poor performance in either spelling or grammar is taken as an indication of poor written communication ability that may detract from your grade.

A grade of A indicates achievement of consistent excellence and distinction throughout the course—that is, conspicuous excellence inall aspects of assignments and discussion in every week.

A grade of B indicates work that meets all course requirements on a level appropriate for graduate academic work. These criteria applyto both undergraduates and graduate students taking the course.

Grades are assigned according to the following percentage ranges:

Score Range	Letter Grade
100-90	= A
89-80	= B
79-70	= C
<70	= F

Final grades will be determined by the following weighting:

Item	% of Grade
Preparation and Participation (Module Discussions)	15%
Problem-set assignments	20%
Cadence assignments	35%
Exams (Midterm + Final)	30% (15% + 15%)

Academic Policies

Deadlines for Adding, Dropping and Withdrawing from Courses

Students may add a course up to one week after the start of the term for that particular course. Students may drop courses according to the drop deadlines outlined in the EP academic calendar (https://ep.jhu.edu/student-services/academic-calendar/). Between the 6th week of the class and prior to the final withdrawal deadline, a student may withdraw from a course with a W on their academic record. A record of the course will remain on the academic record with a W appearing in the grade column to indicate that the student registered and withdrew from the course.

Academic Misconduct Policy

All students are required to read, know, and comply with the Johns Hopkins University Krieger School of Arts and Sciences (KSAS) / Whiting School of Engineering (WSE) Procedures for Handling Allegations of Misconduct by Full-Time and Part-Time Graduate Students.

This policy prohibits academic misconduct, including but not limited to the following: cheating or facilitating cheating; plagiarism; reuse of assignments; unauthorized collaboration; alteration of graded assignments; and unfair competition. Course materials (old assignments, texts, or examinations, etc.) should not be shared unless authorized by the course instructor. Any questions related to this policy should be directed to EP’s academic integrity officer at ep-academic-integrity@jhu.edu.

Students with Disabilities - Accommodations and Accessibility

Johns Hopkins University values diversity and inclusion. We are committed to providing welcoming, equitable, and accessible educational experiences for all students. Students with disabilities (including those with psychological conditions, medical conditions and temporary disabilities) can request accommodations for this course by providing an Accommodation Letter issued by Student Disability Services (SDS). Please request accommodations for this course as early as possible to provide time for effective communication and arrangements.

For further information or to start the process of requesting accommodations, please contact Student Disability Services at Engineering for Professionals, ep-disability-svcs@jhu.edu.

Student Conduct Code

The fundamental purpose of the JHU regulation of student conduct is to promote and to protect the health, safety, welfare, property, and rights of all members of the University community as well as to promote the orderly operation of the University and to safeguard its property and facilities. As members of the University community, students accept certain responsibilities which support the educational mission and create an environment in which all students are afforded the same opportunity to succeed academically.

For a full description of the code please visit the following website: https://studentaffairs.jhu.edu/policies-guidelines/student-code/

Classroom Climate

JHU is committed to creating a classroom environment that values the diversity of experiences and perspectives that all students bring. Everyone has the right to be treated with dignity and respect. Fostering an inclusive climate is important. Research and experience show that students who interact with peers who are different from themselves learn new things and experience tangible educational outcomes. At no time in this learning process should someone be singled out or treated unequally on the basis of any seen or unseen part of their identity.

If you have concerns in this course about harassment, discrimination, or any unequal treatment, or if you seek accommodations or resources, please reach out to the course instructor directly. Reporting will never impact your course grade. You may also share concerns with your program chair, the Assistant Dean for Diversity and Inclusion, or the Office of Institutional Equity. In handling reports, people will protect your privacy as much as possible, but faculty and staff are required to officially report information for some cases (e.g. sexual harassment).

Course Auditing

When a student enrolls in an EP course with “audit” status, the student must reach an understanding with the instructor as to what is required to earn the “audit.” If the student does not meet those expectations, the instructor must notify the EP Registration Team [EP-Registration@exchange.johnshopkins.edu] in order for the student to be retroactively dropped or withdrawn from the course (depending on when the "audit" was requested and in accordance with EP registration deadlines). All lecture content will remain accessible to auditing students, but access to all other course material is left to the discretion of the instructor.