525.642.3VL - FPGA Design Using VHDL

Course Structure

This class is Virtual Live, meaning we will meet online synchronously every Tuesday at 4:30.  Please check the schedule for pre-class and post-class assignments.

Course Topics

• Basic Combinatorial Logic
• VHDL Processes
• Testbenches
• VHDL Data Types
• Operators in Standard Numeric Library
• Finite State Machines (FSMs)
  
• Linear Feedback Shift Registers (LFSRs)
• VHDL Parameterization
• Special Structures and Intellectual Property
• Timing and Power Considerations
• Special Topics

Course Goals

In this course, we will be learning fundamentals of VHDL with an emphasis on coding for synthesis, good digital design practices, and writing test-benches for exercising our designs. Each student will complete a number of assignments using a development board based on the Xilinx Artix 7 FPGA.

Course Learning Outcomes (CLOs)

• Translate a functional system description into appropriate digital blocks coded in VHDL.
• Perform synthesis, place-and-route, and map a digital design onto a target FPGA.
• Describe the behavior and performance of designs targeting FPGAs.
• Implement Finite State Machines (FSMs) to solve digital design problems.
• Utilize the Nexys4 development board to solve common design problems in the Xilinx Vivado environment.
• Simulate the behavior of VHDL designs using test benches written in VHDL and simulated using Vivado Simulator.

Textbooks

not required

Other Materials & Online Resources

Required Hardware

Each registered student will be assigned an FPGA development board at the beginning of the semester. Each student is responsible for getting access to a VGA monitor with VGA cable and an oscilloscope for some of the labs.   Note: If you are registered for the course and receive a development board, you are expected to return the development board to the EP program, when the course completes for the semester or when the student leaves the course.

Required Software

Xilinx Vivado
You will need access to a recent version of Xilinx Vivdao 2016.1 or newer (DO NOT install ISE). You can download the Xilinx Vivado webpack from: http://www.xilinx.com/support/download.html 

Digilent Nexys-4 Board Files
I also recommend installing the Nexys-4 Board files, which can be found here: https://github.com/Digilent/vivado-boards/archive/master.zip

Student Coursework Requirements

Laboratory Assignments (35% of Final Grade Calculation)

• The instructor will give the students the design requirements and the student will construct a design in VHDL. The student will then implement the design on the development board for demonstration.
• Unless otherwise specified, each assignment will count equally towards the cumulative 50% of the class grade.
• Assignments are given to students every week or every other week.  They will be due one or two weeks from the assigned date by class-time, at the beginning of class.

• The first lab is assigned the first day of class and will be due the following week. The tutorial should be completed first, but does not need to be submitted. 
• Lab assignments should be submitted via Canvas (as a .zip). Note: The only files needed for each submission are all the .vhd files, the .xdc file, the .bit file, and a design description, which can be in .doc or .pdf.

• Laboratory assignments can be completed at home using a personal computer and an FPGA development kit, which is provided by the course instructor. The on-campus computers are intended as an alternate means to work on the lab assignments.

• Please note the lab assignments are to be completed independently.  Helping each other with tool related problems, class material, and general VHDL knowledge is encouraged, but copying projects from other students or the internet is considered academic misconduct under university policy (see the university’s Academic Catalog).
• Simply meeting requirements for the demonstration is not 100% of the assignment.  The design should be well organized, have appropriate comments, and effectively use the chip’s resources.  An overall description of the design should be included, including block diagram of the design and resource utilization.

Midterm Exam (35% of Final Grade Calculation)

• Material for the midterm may include all topics in the course presentations, discussed in class, and covered in the laboratory assignments. More details will be given before the exam. Knowledge of VHDL concepts, syntax and behavior are required.

Quizzes (10% of Final Grade Calculation)

• Brief quizzes will be given at the online after every class. The quizzes cover, in a very straight-forward manner, concepts from the previous week’s lecture and/or homework assignments.
• The lowest quiz score will be dropped.

Final Project and Presentation (15% of Final Grade Calculation)

• There will be a final project and presentation assigned after the midterm.
• This will give the student the opportunity to put the skills learned in the class together and potentially tie the knowledge in with applications of interest to the student and his or her work. 
• The presentation gives the students the chance to learn from each other and practice presentation skills.

Participation/ Effort (5% of Final Grade Calculation)

Since this is a graduate level course, some level of independence is expected of the student to meet the requirements of the course. This means that the student is expected to further investigate concepts presented in class and work independently to meet the requirements for each lab assignment. It is left to the instructor’s discretion how to award these points to each student.

Late Submissions

• Late: minus 5 points for every week late starting from the day the lab is due
• After one week after the midterm, late labs will not be accepted
• Lab assignments are considered late if submitted after the due date and time. For example, if an assignment is due at 4:30 pm for a particular day, then it is considered a week late if submitted at 4:31 pm or later.

Grading Policy

EP uses a +/- grading system (see “Grading System”, Graduate Programs catalog, p. 10).

Course Evaluation

Final grades will be determined by the following weighting:

Academic Policies

Deadlines for Adding, Dropping and Withdrawing from Courses

Students may add a course up to one week after the start of the term for that particular course. Students may drop courses according to the drop deadlines outlined in the EP academic calendar (https://ep.jhu.edu/student-services/academic-calendar/). Between the 6th week of the class and prior to the final withdrawal deadline, a student may withdraw from a course with a W on their academic record. A record of the course will remain on the academic record with a W appearing in the grade column to indicate that the student registered and withdrew from the course.

Academic Misconduct Policy

All students are required to read, know, and comply with the Johns Hopkins University Krieger School of Arts and Sciences (KSAS) / Whiting School of Engineering (WSE) Procedures for Handling Allegations of Misconduct by Full-Time and Part-Time Graduate Students.

This policy prohibits academic misconduct, including but not limited to the following: cheating or facilitating cheating; plagiarism; reuse of assignments; unauthorized collaboration; alteration of graded assignments; and unfair competition. Course materials (old assignments, texts, or examinations, etc.) should not be shared unless authorized by the course instructor. Any questions related to this policy should be directed to EP’s academic integrity officer at ep-academic-integrity@jhu.edu.

Students with Disabilities - Accommodations and Accessibility

Johns Hopkins University values diversity and inclusion. We are committed to providing welcoming, equitable, and accessible educational experiences for all students. Students with disabilities (including those with psychological conditions, medical conditions and temporary disabilities) can request accommodations for this course by providing an Accommodation Letter issued by Student Disability Services (SDS). Please request accommodations for this course as early as possible to provide time for effective communication and arrangements.

For further information or to start the process of requesting accommodations, please contact Student Disability Services at Engineering for Professionals, ep-disability-svcs@jhu.edu.

Student Conduct Code

The fundamental purpose of the JHU regulation of student conduct is to promote and to protect the health, safety, welfare, property, and rights of all members of the University community as well as to promote the orderly operation of the University and to safeguard its property and facilities. As members of the University community, students accept certain responsibilities which support the educational mission and create an environment in which all students are afforded the same opportunity to succeed academically. 

For a full description of the code please visit the following website: https://studentaffairs.jhu.edu/policies-guidelines/student-code/

Classroom Climate

JHU is committed to creating a classroom environment that values the diversity of experiences and perspectives that all students bring. Everyone has the right to be treated with dignity and respect. Fostering an inclusive climate is important. Research and experience show that students who interact with peers who are different from themselves learn new things and experience tangible educational outcomes. At no time in this learning process should someone be singled out or treated unequally on the basis of any seen or unseen part of their identity. 
 
If you have concerns in this course about harassment, discrimination, or any unequal treatment, or if you seek accommodations or resources, please reach out to the course instructor directly. Reporting will never impact your course grade. You may also share concerns with your program chair, the Assistant Dean for Diversity and Inclusion, or the Office of Institutional Equity. In handling reports, people will protect your privacy as much as possible, but faculty and staff are required to officially report information for some cases (e.g. sexual harassment).

Course Auditing

When a student enrolls in an EP course with “audit” status, the student must reach an understanding with the instructor as to what is required to earn the “audit.” If the student does not meet those expectations, the instructor must notify the EP Registration Team [EP-Registration@exchange.johnshopkins.edu] in order for the student to be retroactively dropped or withdrawn from the course (depending on when the "audit" was requested and in accordance with EP registration deadlines). All lecture content will remain accessible to auditing students, but access to all other course material is left to the discretion of the instructor.